The fabrication of integrated electronic devices on semiconductor substrates usually requires that circuit topographies, which have been transferred by conventional photolithographic and dry or wet etching techniques, be checked for the occurrence of critical architectures that might impair reliable operation of a formed component. In particular, this test is necessary where a conductive layer is deposited onto a surface less than truly planar, that is, one showing local discontinuities or depressions. In fact, in some cases the conductive layer may have such a slender cross-section due to its poor adhesion on the deposited underlayer as to develop mechanical ruptures resulting in loss of electrical continuity. Accordingly, an integrated electronic device having a plurality of active elements with gate regions extending across the substrate as discrete parallel lines, for example, in the form of floating gate lines, typically requires reduction to a planar architecture prior to receiving a conductive overlayer.
Upon reviewing a vertical cross-section of the above-mentioned semiconductor substrate using an electronic microscope, as shown in FIG. 4, a typical square-wave profile can be observed. For the reasons just given, the square-wave profile is unsuitable to receive a deposition of conductive overlayer.
To avoid such problems, deposition of a conductive layer must be preceded by a planarity optimization step to provide a less discontinuous cross-sectional profile of the semiconductor substrate.
By way of example, consider a topography of the matrix type defined by a plurality of floating gates orthogonally intersected by a plurality of strips of a conductive material. That is, a structure typical of semiconductor storage circuits. In this specific application, the plurality of conductive (polysilicon doped+ONO) parallel lines including the floating gates will be referred to as the "bit lines," and the plurality of conductive (polysilicon doped+WSi.sub.2) strips will be referred to as the "word lines."
In connection with the aforementioned example, a number of problems arise if a planarization step is not carried out prior to forming the plurality of word lines that orthogonally intersect the bit lines.
One problem results from the inherent nature of the conductive layers which, once deposited, tend to distribute themselves non-uniformly across the semiconductor substrates, thereby developing discontinuous profiles where substantially thick areas alternate with thinner areas. This problem is more pronounced when the semiconductor cross-sectional profile is more discontinuous. The deposition areas where the conductive layer is the least thick are the areas most susceptible to mechanical ruptures that destroy the electrical continuity of the layer.
Another problem arises when the plurality of regions in the semiconductor substrate, bounded by the bit lines, must be isolated electrically from the conductive layer deposited. Thermal growth of an isolation oxide in the spaces separating the bit lines may become necessary, which farther diminishes the vertical cross-section of the conductive layer, thereby increasing the resistance associated with the word lines. The word lines are formed from the deposited conductive layer by conventional photolithographic processes and either wet or dry etching operations.
FIG. 8 highlights another problem that is typically associated with devices having a deposited conductive layer. FIG. 8 is a photograph taken by an electronic microscope showing schematically a vertical cross-section of a plurality of bit lines integrated on a semiconductor substrate isolated from one another by a deposition of dielectric oxide and capped with a conductive layer. The problem is illustrated by the dark region located at the bottom of the picture. The dark region represents slenderized areas of the conductive layer near a light region identifying an oxide layer that separates the bit line from the conductive layer. The slenderized areas may cause short circuits between the active regions of the semiconductor substrate located beneath the plurality of bit lines and the word lines.
One more problem is the photolithographic processes and either wet or dry etching operations that are used to form the word lines from the deposited conductive layer may deform the floating gates because of the reiterate flushing involved with thoroughly removing the conductive layer from the regions not masked with resist.
A known proposal for planarizing semiconductor substrates having a plurality of floating gates is disclosed in Patent Application No. VA/000117/IN entitled "Processo EPROM a tovaglia" ("A Tablecloth EPROM Process"), filed by S. Mazzoli, M. Melanotte, L. Masini, and M. Sali in 1989. The patent application proposes isolating the plurality of floating gates from one another by depositing a first dielectric layer of the TetraEthylOrthoSilicate (TEOS) type. The thickness of the TEOS growth layer 13 is quite substantial. FIGS. 5A and 5B show one example of a prior art approach. On top of a substrate 1, a gate oxide 2 is formed on top of which is formed a layer of first poly 3, insulator 4, second poly 5 having a space 7 between. adjacent bit lines, as is well-known in the art. This provides a gate channel region 9 of a bit line 6. A sidewall oxide spacer is then formed, again, as well-known in the art. A TEOS layer 13 is formed, for example, three times as great as the step between the substrate 1 and the upper portion of the individual bit lines.
A second dielectric layer of the Spin-On Glass (SOG) 14 type is then deposited onto the first dielectric layer 13 in order to planarize the surface of the semiconductor substrate. Thereafter, the planarized surface is subjected to selective etching with respect to the polysilicon of the plurality of floating gates, thereby thoroughly removing the SOG dielectric layer and confining the TEOS layer to the gaps between the plurality of floating gates.
However, a serious drawback of this proposal is that the wet or dry etching steps used to remove the excess insulating dielectric are hardly repeatable and cause the planarity previously achieved through the deposition of the SOG type of dielectric layer to deteriorate.
In addition to the drawback mentioned above, the deposition of dielectric layers of the TEOS type are often accompanied by the formation of micro-voids or cracks within the grown material. These micro-voids or cracks may establish undesired contacts between contiguous deposited layers, as previously shown in FIG. 8.
The above observation is confirmed in the article "Planarized SiO.sub.2 Interlayer Formed by Two Step O.sub.3 /TEOS APCVD and Low Temperature Annealing," by Koji Kishimoto, Mieko Suzuki, Takeshi Iirayama, Yasuo Ikeda, and Youichirou Numasawa of NEC Corporation, Jun. 9-10, 1992, page 150, line 10. The authors emphasize the impossibility of using TEOS-type dielectric layers of substantial thickness because of the occurrence of mechanical failures that can only be avoided by adopting more elaborate growth methods.